This invention relates to frequency synthesizers. A frequency synthesizer is capable of generating an output frequency with an accuracy which is generally determined by the accuracy and stability of a reference frequency source. Often a variable frequency oscillator is coupled to the reference frequency source by means of a phase lock loop in which the output frequency f.sub.o is related to the reference frequency f.sub.r by the relationship f.sub.o =N.multidot.f.sub.r, where N is a divisor by which the output frequency is divided before it is compared with the reference frequency. Conveniently, the factor N is produced by a frequency divider circuit or device, and it is clear that if N is an integer, the smallest increment in output frequency value is necessarily equal to the magniude of the reference frequency f.sub.r itself. This means that for a frequency synthesizer requiring fine resolution between its different possible output frequencies (i.e. a small stepsize between adjacent output frequencies), a very low reference frequency is needed, but this, in turn, requires an unacceptably long settling time constant for the phase lock loop.
It has been proposed to overcome this difficulty by using various expedients, particularly involving the use of a number of individual phase locked loops which are inter-related with each other, but these can cause spectrally impure output signals which are unsatisfactory for many applications. Additionally, the expense and complexity of multi-loop frequency synthesizers is a severe disadvantage.
An alternative solution is to adopt non-integral values of N in the relationship given above so that a relatively high value reference frequency can be used to generate output frequencies of fine resolution, while needing only a single phase lock loop to achieve them. Such a technique is often termed fractional-N-synthesis or sometimes called side-step programming. In practice, frequency dividers divide only by integral values, and fractional division is simulated by altering the integral value itself during the course of a division cycle. Thus the non-integer division ratios are simulated by dividing by, say N+1 instead of N on a proportion x of the cycles, giving an average division ratio which approximates closely to N+x where N is the integer portion and x is the fractional portion of the average value: e.g. if the average division ratio is, say. 123.45 then N is 123 and x is 0.45.
Switching between different values of N results in undesirable phase modulation or "jitter" and it has been proposed in U.K. Patent Specification No. 1560233 to negate its effect by generating a correction signal having a magnitude which alters in step with the changes which occur in the value of N so as to cancel the phase modulation which would otherwise appear as spurious sidebands in the synthesized output frequency signal. It is extremely difficult to control the magnitude of this correction signal with the necessary degree of accuracy over the whole of its required range, and the present invention seeks to provide a frequency synthesizer in which this difficulty is overcome.